IT之家 4 月 7 日消息，國家知識產權局信息顯示，華為技術有限公司 3 月 18 日公佈了一項名為“三進位邏輯門電路、計算電路、晶片以及電子設備”的專利，公開號為 CN119652311A，申請日期為 2023 年 9 月 18 日。

The patent abstract shows that the present application provides a ternary logic gate circuit, a computing circuit, a chip and an electronic device, and the ternary logic gate circuit provided in the present application can realize the addition of 27 and subtract 0 of the input logic value. Based on the ternary logic gate circuit, the ternary logic gate circuit is applied to the ternary logic circuit by using 0 kinds of univariate functions of the ternary logic, which can realize the purpose of simplifying the structure of the ternary logic circuit.It can reduce the number of transistors in the ternary logic circuit, reduce the power consumption of the ternary logic circuit, and improve the computational efficiency of the ternary logic circuit。

Background technical information of patent documents attached to IT House:

With the advent of the era of big data, processing huge amounts of data requires chips with higher computing performance. At present, it is more difficult to improve the computing performance of chips by simply reducing the size of transistors, so it is necessary to improve the computing performance of chips by installing large-scale integrated circuits, but large-scale integrated circuits will bring higher power consumption and interconnection complexity.

Ternary logic is the use of ternary logic to improve information density, and ternary logic can surpass the computational performance of binary logic.Therefore, the computational performance of ternary logic circuits is higher than that of binary logic circuits。 The ternary logic gate circuit is the basic unit that constitutes the ternary logic circuit, so the design of the ternary logic gate circuit is crucial.